d1u54-d-650-12-hbxc series 54mm 1u front end dc-dc power su pp l y converter d1u54-d-650-12-hbxc.a02 page 1 of 9 www .murata- p s.com/su pp ort www .murata- ps.com / en / 3d / acdc.htm l www .murata-ps.com / en / 3d / acdc.htm l www .murata- p s.com/en/3d/acdc.html www .murata-ps.com / en / 3d / acdc.htm l ww w .murata - p s.com/en/3d/acdc.htm l product overview the d1u54-d-650-12-hbxc products are very high ef?ciency dc input 650 watt front end supplies provided with a 12v main and a 12v standby output. an ac tive (analogue) current share characterist ic is provided to allow units to be operated in parallel. the power supply may be hot plugged; recovers from ov ertemperature faults, and has status leds on the front panel in addition to hardware signal lo gic and pmbus? status signals. the low pro?le 1u package and 21.4w/cubic inch power density make them ideal for delivering reliable, ef?cient power to networking equipment, workstations, storage systems and other 12v distributed power architectures. ordering guide part number murata internal part number power output -44 to -72vdc main output standby output air?ow d1u54-d-650-12-hb3c m1879 650w 12vdc 12vdc front to back d1u54-d-650-12-hb4c m1878 back to front features ? 650w output powe r ? 93% ef?ciency at 50% load ? 12v main output ? 12v standby output ? 1u height: ? 2.15" x 9.00" x 1.57" ? 54.5mm x 228.6mm x 40mm ? 21.4 watts per cubic inch density ? n+1 redundancy capable, including hot plugging ? a ctive (analogue) current sharing on 12v main output; or ing fet ? overvoltage, overcurrent, overtemperature protection ? internal cooling fan (variable speed) ? pmbus?/i2c interface with status indicators ? rohs compliant ? two year warranty available now at: www.murata-ps.com/en/3d/acdc.html input characteristics parameter conditions min. nom. max. units input source voltage operating range -44 -53 -72 vdc turn-on input voltage ramp up -42.5 -43 -43.5 vdc turn-off input voltage ramp down -37.5 -38 -39.5 input current at vin = -53vdc 650w 13.6 adc inrush current cold start (25c) between 0 to 200ms 25 apk ef?ciency (-53vdc) excluding fan load 20% load 90 % 50% load 93 100% load 92 output voltage characteristics nominal output voltage parameter conditions min. typ. max. units 12v output set point accuracy 50% load; tamb =25c 11.96 12.00 12.04 vdc line and load regulation setpoint; temperature; line and load -1.0% +1.0 % % ripple voltage & noise 1, 2 20mhz bandwidth 120 mv p-p output current range 0 54.2 a load capacitance 500 4000 f 12vsb output set point accuracy 50% load; tamb = 25c 11.96 12.00 12.04 vdc line and load regulation setpoint; temperature; line and load 11.7 12.3 ripple voltage & noise 1 20mhz bandwidth 120 mv p-p output current 0 2 a 1 ripple and noise is measured with a parallel combination 0.1f of ceramic and 10f of tantalum capacitance on each measurement node. 2 measurements assume the use of the minimum load capacitance as specified for the main 12v output and a minimum load of 5%. below 5% loading the overall voltage deviation shall be within 2.5%. t est certificate and test report for full details go to www .murata-ps.com/rohs cb
d1u54-d-650-12-hbxc series 54mm 1u front end dc-dc power su pp l y converter d1u54-d-650-12-hbxc.a02 page 2 of 9 www .murata- p s.com/su pp ort 0 50 100 150 200 250 02468 back pressure (pa) psu airflow (cfm) d1u54-d-650-12-hbxc p & q curve airflow front to back airflow back to front output characteristics parameter conditions min. typ. max. units startup time dc ramp up 3 s transient response main 12v, 50% load step, 1a/s di/dt 5 500 % s 12vsb, 50% load step, 1a/s di/dt current sharing accuracy >10% load; *of maximum output current capability 5* % hot swap transients all outputs remain in regulation 5 % holdup time (total effective ho ld up - see timing waveforms) full dc input source range; 100% load 2 4 ms environmental characteristics parameter conditions min. typ. max. units storage temperature range -40 70 c operating temperature range -5 50 operating humidity noncondensing; +45c 5 90 % stora g e humidit y 5 95 a ltitude (without derating at 40c) 3000 m shoc k 30g non-operating operational vibration sine sweep; 5-200hz, 2g; random vibration , 5-500hz , 1.11g mtbf(target) per telcordia sr-332 issue 3 m1c3 @40c 619k hrs safety approvals can/csa c22.2 no 60950-1-07, am.1:2011 ul 60950-1-2011, 2nd ed. iec60950-1:2005 (2nd ed.) w a1:2009 en 60950-1:2006+a11+a1+a12+a2 ccc gb4943.1-2011; gb9254-1-2008; gb17625, 1-2012 input fuse power supply has an internal 25a/100vdc fast blow fuse in the dc input negative line. weight 1.74 lbs (0.789 kg) airflow; pressure vs. flow (pq) curves d1u54-d-650-12-hb3c & d1u54-d-650-12-hb4c notes: 1. the above curves represent performance base d upon a the use of a 20mm thickness fan. 2. curves recorded at room ambient (circa 25c). 3. curves generated with intermal fan running at 100% duty cycle
d1u54-d-650-12-hbxc series 54mm 1u front end dc-dc power su pp l y converter d1u54-d-650-12-hbxc.a02 page 3 of 9 www .murata- p s.com/su pp ort protection characteristics output parameter conditions min. typ. max. units overtemperature autorestart with 4c hysteresis fo r recovery (warning issued at 70c) 75 c 12v overvoltage latching 13 14.5 c overcurrent (target) the output shall shutdown when an overcurrent condition is detected. it will auto restart after 1sec; howeve r if the overcurrent condition is rede tected the output will once again shutdown. the output will once again re-start, however if the overcu rrent condition persists it will latch of after the fifth unsuccessful attempt. to reset the latch it will be necessary to toggle the ps_on_l signal (b4) or recycle the incoming dc source. 60 70 a 12vsb overvoltage latching 13.0 14.5 v overcurrent the output shall shutdown when an overcurrent is detected. it will auto restart after 2sec; however if the overcurr ent is re-detected the output will once again shutdown. this cycle will occur indefinitely while the overcurrent condition persists. 2.2 2.8 a isolation characteristics parameter conditions min. typ. max. units insulation safety rating input to output 1000 vdc input to chassis 1000 vdc isolation output to chassis 500 vdc emissions and immunity conducted emissions fcc 47 cfr part 15/cispr 22/en55022 class a with 6db margin esd immunity iec/en 61000-4-2 level 4 criteria a radiated field immunity iec/en 61000-4-3 level 3 criteria b electrical fast transients/burst immunity iec/en 61000-4-4 level 3 criteria b surge immunity iec/en 61000-4-5 1kv common mode and differential mo de, unit passes criteria a (normal performance)* rf conducted immunity iec/en 61000-4-6 level 3 criteria a magnetic field immunity iec/en 61000-4-8 3 a/m criteria b voltage dips, interruptions ---- -53vin, 80% load, dip 100% duration 4ms,criteria (a) * impedance is 2 ohms for differential and common mode. status indicators led name led mode led state/operation description input ok solid green input voltage oper ating within normal specified range input ov/uv warning blinking gree n input voltage operating in: 1) overvoltage warning, or 2) undervoltage warning range input off or fault off input voltage operating: 1) above overvoltage range, or 2) below undervoltage range, or 3) not present output power good solid green main output and standby output enabled with no power supply warning or fault detected output standby blinking green standby output enable d with no power supply warning or fault detected output warning blinking amber power supply warning detected as pe r pmbus status_x reporting bytes ? output fault solid amber power supply fault detected as pe r pmbus status_x reporting bytes ? ? led fault/warning operation follows pmbus fault/warning reporting status flags and will thus also be 'sticky' (i.e. even if act ual fault/warning is cleared, led will still be in fault or warning mode until pmbus status flags are cleared with the clear_faults command
d1u54-d-650-12-hbxc series 54mm 1u front end dc-dc power su pp l y converter d1u54-d-650-12-hbxc.a02 page 4 of 9 www .murata- p s.com/su pp ort status and control signals signal name i/o description interface details input_ok (dc source) output the signal output is driven high wh en the input source is availabl e and within acceptable limits. the output is driven low to i ndicate loss of input power. there is a minimum of 5ms pre-wa rning time before signal changes to a high impedance state or is driven low to indicate loss of 12v. the powe r supply must ensure that this interface signal provides accurate status when dc power is lost. pulled up internally via 10k to 3.3vdc. a logic high >2.0vdc; a logic low <0.8vdc driven low by intern al cmos buffer (open drain output). pw_ok (output ok) output the signal is asse rted, driven high, by the power supply to indicate that all outputs are valid. if an y of the outputs fail then this output will be hi-z or driven low. the output is driven low to indicate that the main output is outsid e of lower limit of regulation. pulled up internally via 10k to 3.3vdc. a logic high >2.0vdc; a logic low <0.8vdc driven low by intern al cmos buffer (open drain output). smb_alert (fault/warning) output the signal output is driven low to indicate that the power supply has detected a warning or fault and is intended to alert the system. this output mu st be driven high when the power is operating correctly (within specified limits). the signal will revert to a high level when the warning/fault stimulus (that caused the alert) is removed. pulled up internally via 10k to 3.3vdc. a logic high >2.0vdc;a logic low <0.8vdc driven low by intern al cmos buffer (open drain output). present_l (power supply absent) output the signal is used to detect the presence (i nstalled) of a psu by the host system. the signal is connected to psu logic sgnd within the power module. passive connection to +vsb_return. a logic low <0.8vdc ps_on (power supply enable/disable input this signal is pulled up internally to the inte rnal housekeeping supply (w ithin the power supply). the power supply main 12vdc output will be enabled when this signal is pulled low to +vsb_return. in the low state the signal input shall not source more than 1ma of current. the 12vdc output will be disabled when the input is driven higher than 2.4v, or open circuited. cycling this signal shall clear latched fault conditions. pulled up internally via 10k to 3.3vdc. a logic high >2.0vdc a logic low <0.8vdc input is via cmos schmitt trigger buffer. ps_kill input this signal is used duri ng hot swap to disable the main outp ut during hot swap extraction. the input is pulled up internally to the internal housekeeping supply (withi n the power supply). the signal is provided on a short (lagging pin) and should be connected to +vsb_return. pulled up internally via 10k to 3.3vdc. a logic high >2.0vdc; a logic low <0.8vdc input is via cmos schmitt trigger buffer. addr (address select) input an analogue input that is used to set the address of the inte rnal slave devices (eeprom and microprocessor) used for digital communications. connection of a suitable resistor to +vsb_return, in conjunction with an internal resistor divider chain, will configure the required address (see addr address selection table). dc voltage between the limits of 0 and +3.3vdc. scl (serial clock) both a serial clock line compatible with pmbus tm power systems management protocol part 1 C general requirements rev 1.1. no additional internal capacitance is adde d that would affect the speed of the bus. the signal is provided with a series isolator devi ce to disconnect the inte rnal power supply bus in the event that the power module is completely unpowered, v il is 0.8v maximum v ol is 0.4v maximum when sinking 3ma v ih is 2.1v minimum sda (serial data) both a serial data line compatible with pmbus tm power systems management protocol part 1 C general requirements rev 1.1. the signal is provided with a series isolator devi ce to disconnect the inte rnal power supply bus in the event that the power modul e is completely unpowered, v il is 0.8v maximum v ol is 0.4v maximum when sinking 3ma v ih is 2.1v minimum v1_sense v1sense_rtn input remote sense connections inte nded to be connected at and sense the voltage at the point of load. the voltage sense will interact with the internal module regulation loop to compensate for voltage drops due to connection resistance betw een the output connector and the load. if remote sense compensation is not required then the voltage shall be configured for local sense by: 1. v1_sense directly connected to power blades 6 to 10 (inclusive) 2. v1_sense_rtn directly connected to power blades 1 to 5 (inclusive) compensation for up to 0.12vdc total connection drop (output and return connections). ishare bi- directiona l a nalogue bus the current sharing signal is connected between sh aring units (forming an ishare bus). it is an input and/or an output (bi-directional analogue bus) as the voltage on the line controls the current share between sharing units. a power suppl y will respond to a change in this voltage but a power supply can also change the voltag e depending on the load drawn from it. on a single unit the voltage on the pin (and the commo n ishare bus would read 8vdc at 100% load (module capability). for two identical units shar ing the same 100% load this would read 4vdc for perfect current sharing (i.e. 50% module load capability per unit). analogue voltage: +8v maximum; 10k to +12v_rtn
d1u54-d-650-12-hbxc series 54mm 1u front end dc-dc power su pp l y converter d1u54-d-650-12-hbxc.a02 page 5 of 9 www .murata- p s.com/su pp ort timing specifications turn-on delay & output rise time: power-on-delay, risetime, and signaling v1 ps_on delay dc input dc input vsb vsb vsb risetime v1 vsb power-on-delay v1 v1 risetime v1 power-on-delay v1 ps_on delay ps_on ps_on input_ok delay input_ok input_ok pwok delay pwok pwok 1. the turn-on delay after application of ac input within the operating range shall as defined in the following tables. 2. the output rise times shall be measured from 10% of the nominal output to the lower limit of the regulation band as defined in the following tables. time min max v sb rise time 70ms 170ms v 1 rise time 120ms 220ms v sb power-on-delay 300ms 700ms v 1 power-on-delay 500ms 1500ms v 1 ps_on delay 100ms 300ms v 1 pwok delay 300ms 450ms dcok (input) detect 500ms 1000ms timing specifications turn-off (shutdown by ps_on) vsb v1 v1 ps_off delay v1 falltime ps_on input_ok pw_ok delayoff pwok turn-off timing min max notes v1 fall time - - must be monotonic v1 ps_off delay 0ms 6ms pw_ok delay off 2.0ms 1. note this characteristic is applicable for the main 12vdc output shutdown from ps_on pulled high.
d1u54-d-650-12-hbxc series 54mm 1u front end dc-dc power su pp l y converter d1u54-d-650-12-hbxc.a02 page 6 of 9 www .murata- p s.com/su pp ort timing specifications power removal holdup power removal timing min max notes vsb holdup 20ms 50ms +vsb full load v1 holdup (total effective) 4ms - 100% load dc (input) fail detect 400s 1000s pwok delay off 2.0ms 100% load pwok hold up 2.0ms 4.0ms output connector & signal interface; fci pn 10122460-005lf nb: reference to 3 in column 5, refers to the shortest level signal pin; the shor test pins are the last to make, first to break in the mating sequence.
d1u54-d-650-12-hbxc series 54mm 1u front end dc-dc power su pp l y converter d1u54-d-650-12-hbxc.a02 page 7 of 9 www .murata- p s.com/su pp ort 6, 7, 8, 9, 10 v1 (+12vout) +12v main output 1, 2, 3, 4, 5 +12v rtn/pgnd +12v main output return a1 +vsb standby output b1 +vsb standby output c1 +vsb standby output d1 +vsb standby output e1 +vsb standby output a2 +vsb_return standby output return b2 +vsb_return standby output return c2 unused no end user connection d2 unused no end user connection e2 unused no end user connection a3 aps i 2 c address protocol selection; (select address by appropriate pull down resistor C see table below) b3 unused no end user connection c3 sda i 2 c serial data line d3 v1_sense_r -ve remote sense return e3 v1_sense +ve remote sense a4 scl i 2 c serial clock line b4 ps_on_l remote on/o ff (enable/disable) c4 smb_alert alert signal to host system d4 unused no end user connection e4 input_ok dc input source present & ok a5 ps_kill power supply kill; short pin b5 ishare active current share bus c5 pw_ok power ok; short pin d5 unused no end user connection e5 present_l power module present; short pin wirin mating connector part number description te connectivity 2-1926739-5 fci 10108888-r10253sl f right angle right angle aps address selection aps pin (a3) resistor to gnd (k-ohm)* power supply main controller (serial communications slave address) power supply external eeprom (serial communications slave address) 0.82 0xb0 0xa0 2.7 0xb2 0xa2 5.6 0xb4 0xa4 8.2 0xb6 0xa6 15 0xb8 0xa8 27 0xba 0xaa 56 0xbc 0xac 180 0xbe 0xae * the resistor shall be +/-5% tolerance output connector pin assig nments - d1u54p-w-650-12-hbxc (power supply) fci pn 10122460-005lf pin signal name comments
d1u54-d-650-12-hbxc series 54mm 1u front end dc-dc power su pp l y converter d1u54-d-650-12-hbxc.a02 page 8 of 9 www .murata- p s.com/su pp ort wiring diagram for output wiring diagram for output current share notes 1. main output: current sharing is achieved usi ng the active (analogue) current share method. 2. current sharing can be achieved with or without the remote (v_sense and v_ sense_r) connected to the common load. 3. +vsb outputs can be tied together for redundancy but total combined output power must not exceed the rated standby power. the + vsb output has an internal or ing mosfet for additional redundancy/internal short protection. 4. the current sharing pin b5 is connected betw een sharing units (forming an ishare bus). it is an input and/or an output (bi-dire ctional analogue bus) as the voltage on the line controls the current share between shar ing units. a power supply will respond to a change in this voltage but a power supp ly can also change the voltage depending on the load drawn from it. on a single uni t the voltage on the pin (and the common isha re bus would read 8vdc at 100% (power mo dule load capability). for two units sharing the same 100% load this would read 4vdc for perfect current sharing (i.e. 50% power module load capability per unit). the load for both the main 12v and the vsb rails at initial star tup shall not be allowed to exceed the capability of a single u nit. the load can be increased after a delay of 3sec (minimum), to allow all sharing uni ts to achieve steady state regulation.
d1u54-d-650-12-hbxc series 54mm 1u front end dc-dc power su pp l y converter d1u54-d-650-12-hbxc.a02 page 9 of 9 www .murata- p s.com/su pp ort mechanical dimensions 1. dc input connector: dinkle terminal block, dinkle enterprise: part no. dt-7c-b14w-02 2. dimensions: 2.15" x 9.00" x 1.57" [54.5mm x 228.6mm x 40.0mm] 3. this drawing is a graphical representation of the product and may not show all fine details. 4. reference file: d1u54-d-650-12-hbxc (m1878-m1879)_dra wing for product datasheet_20151216.pdf optional accessories description part number 12v d1u54p output connector card d1u54p-12-conc application notes document number description link acan-64 d1u54p output connector card http://power.murata.com/datasheet?/data/apnotes/acan-64.pdf ACAN-60 d1u54-x communication protocol http://power.murata.com/datasheet?/data/apnotes/ACAN-60.pdf murata power solutions, inc. 11 cabot boulevard, mans?eld, ma 02048 -1151 u.s.a. iso 9001 and 14001 registered this product is subject to the following operating requirements and the life and safety critical application sales policy: refer to: http://www.murata-ps.com/requirements/ murata power solutions, inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. the descriptions contained herein do not imply the g ranting of licenses to make, use, or sell equipment constructed in accordance therewith. speci?cations are subject to change without notice. ? 2016 murata power solutions, inc.
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